It is well understood that extensive testing of hybrid multichip boards is necessary. In recent times, the trend has been to miniaturize chips and chip circuits per se and such miniaturization has enabled the industry to locate more and more circuits on a single chip and more chips on a hybrid multichip board. The foregoing is evidenced by the popularity of VLSI circuits. On the other hand, the manufacture and packing of such circuits gives rise to all kinds of possible infirmities. The detection of those infirmities, prior to the release of the multichip or multicircuit boards for commercial use, understandably, has a very high priority. In the prior art, the circuit designer would design the circuit and then decide how it should be tested. He would generate a truth table or truth tables and establish parameters which define the nature of the test or tests. If the tests were to be performed at a remote chip manufacturer's location, the preferred test information would be sent along to the manufacturer by way of final form truth table information and stored on a magnetic tape or by some other form of mass storage. The time required to generate the tape information, in the early prior art format was not a prohibitive burden to the preparation of the method of testing at the manufacturer's location. However, as the number of circuits have increased on the chip and multicircuit board, testing itself has become more sophisticated and more of a problem than the design of the circuits. For instance, the truth tables required to define the test on a particular chip have become more numerous simply because there were more circuits located on a chip. Accordingly, the amount of time necessary to generate the truth table and test data information and the amount of memory storage required to handle such test information has become significant. When such test information was sent electronically from the design location to the manufacturer's location, it represented a significant burden on the transmission facilities and a burden to store such information at the received end.
The present method and system enables truth table and test data information to be transmitted in compacted form and reconstructed in its final usable form at the receiving end (the manufacturer's location). Accordingly, the transmission facilities are not burdened as was the case in the prior art nor is the storage capability at the receiving end as burdened. Further, the compacted standardized format and procedure enables different design locations to communicate directly with the same or different chip manufacturing locations while assuring complete uniformity and interchangeability of components and end products.
Heretofore at least Texas Instruments, Inc., a chip manufacturer, has prepared standardized test procedures in a form referred to as Test Description Language or TDL. This back end program has enabled designers of T.I. chips to more uniformly define test to be performed on their chips. It would be desirable to provide a system which would compact the test information at the front end in a format that could be expanded at the manufacturer's site for direct use with numerous test platforms made by different manufacturers.